1. Field of the Invention
The present invention relates to a method and apparatus for transferring information among a plurality of data processing devices. More particularly, the present invention relates to an improved computer bus utilizing both source synchronized data transfers and globally synchronized transfers of arbitration and consistency information which eliminates resynchronization and metastability.
2. Art Background
In the computing industry it is quite common to transfer information among a plurality of data processing devices such as processors, memories, input/output devices, peripheral controllers, and the like, on a system bus. A system bus is essentially a collection of wires which connects the various devices together in a prescribed fashion. Typically, a system bus includes address lines, data lines, clock lines, power lines, and a number of control signal lines. Frequently, access to the system bus, as a shared resource, must be arbitrated, and a bus protocol or "handshake" routine is observed by all data processing devices coupled to the bus. Such a bus protocol requires a predetermined sequence of events to take place prior to the actual exchange of data between devices coupled to the bus.
The overall speed and performance of a particular data processing system is greatly influenced by the design and method of operation utilized by its system bus. Two measures of system bus performance are latency and throughput. Latency is the time delay between a device's request to use the bus and an arbiter's granting of that request. Throughput refers to the rate at which a device can transmit data on the bus once it has been granted the right to do so.
Typically, the data corresponding to one bus access request is transmitted in a multi-cycle packet, because the number of bits of information to be transmitted is many times the number of bus wires used for transmitting data. It is desirable that data transmission have high throughput. Arbitration and cache consistency information, however, represent only a few bits of information per bus access, and enough bus wires are typically provided to transmit this information in one or two cycles. For this information, therefore, low latency is more important than high throughput.
It is, therefore, desirable to have a bus with low latency and high throughput to minimize the amount of computing time required for a particular data processing task. With the increased use of multiprocessing, it is further important that a bus apparatus and method of operation support multiprocessing.
Data transfer over a bus can be accomplished utilizing globally synchronized data transfers or source synchronized data transfers. In a globally synchronized data transfer, a central global clock provides the clocking to all devices, including the device sending the data and the device receiving the data. In contrast, in a source synchronized data transfer, the device sending the data sends both the data and the clock signal to the receiving device. In a source synchronized data transfer, the data is frequently stored in a data buffer within the receiving device using the received clock until the receiving device is ready to read the data. When the data is read from this data buffer, it is read out under the control of a local clock on the receiving device. In the prior art, such a process has typically required resynchronization with the attendant risk of metastability.
As will be described, the apparatus and method of the present invention advantageously utilizes high-speed, source synchronized data transfers and lower-speed, globally synchronized transfers of arbitration and consistency information. The bus of the present invention supports cache-coherent multiprocessing, and is advantageously utilized within a packet switched protocol. Further, the method and apparatus of the present invention effectively eliminates the possibility of metastability associated with resynchronization.